Verification of Plc Programs Using Formal Proof Techniques

نویسندگان

  • Andre Sülflow
  • Rolf Drechsler
چکیده

The application of Programmable Logic Controllers (PLCs) in safety critical systems demands a failure free behavior considering all possible scenarios. Due to the cost of software development a user program is often in use on different types of PLCs. But one open question is: Behaves the user program equivalent on all PLCs? We propose a framework suitable to prove the equivalence of a user program regarding different types of PLCs. The semantic behavior of the hardware is embedded and the equivalence against a high level reference model is proved. We apply formal Equivalence Checking (EC) using Boolean satisfiability (SAT) and evaluate the framework in a case study.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

An algebraic approach for PLC programs verification

This article presents a verification based on a specific Boolean algebra, called , and symbolic reasoning on equations defined in this algebra. The formal definition of this algebra enables to model binary signals that include variables states, events, as well as physical delays between events. The behavior of the generic function blocks of the IEC 61131 standard as well as of PLC programs usin...

متن کامل

Simulation and Formal Verification of Industrial Systems Controllers

Actually, the safety control is one of the most important aspects studied by the international researchers, in the field of design and development of automated production systems due to social (avoid work accidents, ...), economics (machine stop time reduction, increase of productivity,...) and technological aspects (less risks of damage of the components,...). Some researchers of the Engineeri...

متن کامل

Elaboration of invariant safety properties from fault-tree analysis

Formal verification of PLC programs using model-checking requires to elaborate previously temporal logic formulae that state in a formal way the properties that must be checked. Unfortunately temporal logic is a formalism totally unknown by automation engineers. This explains why PLC programs developers willing to verify the behavior of their programs are unable to use the existing modelcheckin...

متن کامل

Improving large-sized PLC programs

This paper proposes a formal representation of logic controllers programs that is aiming at improving scalability of model-checking techniques, when verifying controllers extrinsic properties. This representation includes only the states which are meaningful for properties proof and minimizes the number of variables that feature each state. Comparison with previously proposed representations, o...

متن کامل

Automation of Formal Verification of PLC Programs Written in IL

Providing proof of correctness is of the utmost importance for safety-critical systems, many of which are based on Programmable Logic Controllers (PLCs). One widely used programming language for PLCs is Instruction List (IL). This paper presents a tool for the fully automated transformation of IL programs into models of the NuSMV (New Symbolic Model Verifier) model checker. For this, the tool n...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2008